In recent years, serial data transmission has been used for various fields, such as optical communication (PON: passive optical network) shown in FIG. 1, and backplane transmission of a personal computer (PC) or a server, and there is a demand for an increase in the transmission speed of serial data with an increase in the amount of information treated. In order to transmit serial data at a high speed, a clock data recovery circuit (CDR) that extracts phase information from the transmitted serial data and generates a clock in synchronization with data is needed. In addition, various protocols, such as GPON, are used to transmit serial data at a high speed, and they have predetermined transmission rates. In addition, the same protocol, such as Ethernet, may have plural transmission rates. Therefore, in order to standardize a protocol using one LSI, a clock data recovery circuit corresponding to a multi-rate is needed.
JP-A-2007-36869 discloses a serializer/de-serializer circuit (Serdes) including a clock data recovery circuit. The Serdes circuit includes a general clock data recovery circuit, and a parallel-serial conversion circuit, a serial-parallel conversion circuit, and a FIFO (first in first out) circuit are integrated, thereby reducing the size and the power consumption of the circuit.
FIG. 6 is a diagram illustrating a clock data recovery circuit (CDR) included in the serializer/de-serializer circuit (Serdes) shown in FIG. 7 in JP-A-2007-36869. FIG. 6 shows a phase-locked loop 6101 (PLL), a divider 6103, an interpolator 6102 (IP), a sampling circuit 6104 (Spl), and a clock data recovery circuit controller 6106 (CDRctrl: CDR controller).
The divider 6103 (DIV) divides a clock generated by the phase-locked loop 6101 (PLL) into multi-phase clocks. The interpolator 6102 (IP) uses the multi-phase clocks to generate a recovery clock. The sampling circuit 6104 (Spl) compares input data with the recovery clock. The CDR controller 6106 controls the phase of the interpolator 6102 on the basis of the comparison result to generate a recovery clock that is most suitable for the input data.
In FIG. 6, it is possible to correspond to a multi-rate by changing the division ratio of the divider 6103 (DIV) provided between the phase-locked loop 6101 (PLL) and the interpolator 6102 (IP). However, in this method, it is necessary to change the operation speed of the interpolator 6102 (IP) according to the transmission rate of input data, and the interpolator 6102 (IP) needs to have a very large bandwidth. However, when the bandwidth of an analog circuit, such as the interpolator, is increased, jitter or a circuit size is increased.